SH7730 Datasheet, PDF (807/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Figure 23.13 shows sample SCIFA initialization flowcharts.
Initialization
Clear TE and RE bits in SCASCR to 0
Set TFRST bit in SCAFCR to 1 1
Set CKE[1:0] bits in SCASCR
(leaving TE and RE bits cleared to 0)
2
Set CA bit in SCASMR to 1
Set CKS[1:0] bits
3
Set value in SCABRR
4
Clear TFRST bit to 0
5
Set transmit trigger number in
TTRG[1:0] in SCAFCR, write transmit
data exceeding the transmission ⁶
trigger number, and clear TDFE flag
to 0 after reading 1 from it
Wait
1. Be sure to set the TFRST bit in
SCAFCR to 1, to reset the FIFOs.
2. Set the clock selection in SCASCR.
Be sure to clear bits RIE, TIE, TE,
and RE to 0.
3. Set the clock source selection in
SCASMR.
4. Write a value corresponding to the
bit rate into SCABRR.
5. Clear the TFRST bit in SCAFCR to 0.
6. Set the transmit trigger number,
write transmit data exceeding the
transmit trigger number, and
clear the TDFE flag to 0 after reading
it.
7. Wait one bit interval.
1-bit interval elapsed?
Yes
End
7
No
Figure 23.13 Sample SCIFA Initialization Flowchart (1) (Transmission)
Rev. 1.00 Sep. 19, 2007 Page 759 of 1136
REJ09B0359-0100