SH7730 Datasheet, PDF (38/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Figure 28.15 Port R .................................................................................................................... 913
Figure 28.16 Port S..................................................................................................................... 915
Figure 28.17 Port T..................................................................................................................... 917
Section 30 User Break Controller (UBC)
Figure 30.1 Block Diagram of UBC........................................................................................... 976
Figure 30.2 Flowchart of User Break Debugging Support Function ........................................ 1003
Section 31 User Debugging Interface (H-UDI)
Figure 31.1 H-UDI Block Diagram .......................................................................................... 1012
Figure 31.2 TAP Controller State Transitions .......................................................................... 1020
Figure 31.3 H-UDI Reset.......................................................................................................... 1021
Section 33 Electrical Characteristics
Figure 33.1 EXTAL Clock Input Timing ................................................................................. 1062
Figure 33.2 CKIO Clock Output Timing.................................................................................. 1062
Figure 33.3 Power-On Oscillation Settling Time ..................................................................... 1062
Figure 33.4 Reset Input Timing................................................................................................ 1063
Figure 33.5 Interrupt Signal Input Timing................................................................................ 1064
Figure 33.6 Bus Release Timing .............................................................................................. 1064
Figure 33.7 Pin Drive Timing at Standby................................................................................. 1065
Figure 33.8 Basic Bus Cycle in Normal Space (No Wait)........................................................ 1068
Figure 33.9 Basic Bus Cycle in Normal Space (Software Wait 1) ........................................... 1069
Figure 33.10 Basic Bus Cycle in Normal Space (Asynchronous External Wait 1 Input)......... 1070
Figure 33.11 Basic Bus Cycle in Normal Space
(Software Wait 1, Asynchronous External Wait Valid (WM Bit = 0),
No Idle Cycle)..................................................................................................... 1071
Figure 33.12 CS Extended Bus Cycle in Normal Space
(CSnWCR.SW[1:0]=B'01, CSnWCR.HW[1:0]=B'01, External Wait 1
Input)................................................................................................................... 1072
Figure 33.13 Bus Cycle of SRAM with Byte Selection
(CSnWCR.SW[1:0]=B'01, CSnWCR.HW[1:0]=B'01, External Wait 1 Input,
BAS = 0 (UB and LB in Write Cycle Controlled))............................................. 1073
Figure 33.14 Bus Cycle of SRAM with Byte Selection (CSnWCR.SW[1:0]=B'01,
CSnWCR.HW[1:0]=B'01, External Wait 1 Input, BAS = 1
(WE in Write Cycle Controlled))........................................................................ 1074
Figure 33.15 Read Bus Cycle of Burst ROM (Software Wait 1, Asynchronous External
Wait 1 Input, Burst Wait 1, Number of Burst = 2).............................................. 1075
Figure 33.16 Single Read Bus Cycle of SDRAM (Auto Precharge Mode, CAS Latency 2,
TRCD = 1 Cycle, TRP = 1 Cycle) ...................................................................... 1076
Figure 33.17 Single Read Bus Cycle of SDRAM (Auto Precharge Mode, CAS Latency 2,
TRCD = 2 Cycles, TRP = 2 Cycles) ................................................................... 1077
Rev. 1.00 Sep. 19, 2007 Page xxxviii of xlviii