SH7730 Datasheet, PDF (579/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 17 Realtime Clock (RTC)
17.3.9 Second Alarm Register (RSECAR)
RSECAR is an alarm register corresponding to the BCD coded second counter RSECCNT of the
RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From
among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and
alarm register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The range of second alarm, which can be set, is 00 to 59 (decimal) + ENB bits. Errant operation
will result if any other value is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields
are not initialized by a power-on reset or manual reset, or in standby mode.
Bit: 7
6
5
4
3
2
1
0
ENB 10-second units
1-second units
Initial value: 0 — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6 to 4
3 to 0
Initial
Bit Name Value
R/W
ENB
0
R/W

Undefined R/W

Undefined R/W
Description
When this bit is set to 1, a comparison with the
RSECCNT value is performed.
Ten’s position of seconds setting value
One’s position of seconds setting value
Rev. 1.00 Sep. 19, 2007 Page 531 of 1136
REJ09B0359-0100