SH7730 Datasheet, PDF (689/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
(2) Transmit/Receive Timing
The SIOFTXD transmit timing and SIOFRXD receive timing relative to the SIOFSCK can be set
as the sampling timing in the following two ways. The transmit/receive timing is set using the
REDG bit in SIMDR.
• Falling-edge sampling
• Rising-edge sampling
Figure 21.4 shows the transmit/receive timing.
(a) Falling-edge sampling
SIOFSCK
SIOFSYNC
SIOFTXD
SIOFRXD
Receive timing
Transmit timing
(b) Rising-edge sampling
SIOFSCK
SIOFSYNC
SIOFTXD
SIOFRXD
Figure 21.4 SIOF Transmit/Receive Timing
Receive timing
Transmit timing
21.4.3 Transfer Data Format
The SIOF performs the following transfer.
• Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data
• Control data: Transfer of 16-bit data (uses the specific register as interface)
(1) Transfer Mode
The SIOF supports the following four transfer modes as listed in table 21.6. The transfer mode can
be specified by the bits TRMD[1:0] in SIMDR.
Table 21.6 Serial Transfer Modes
Transfer Mode
Slave mode 1
Slave mode 2
Master mode 1
Master mode 2
SIOFSYNC
Synchronous pulse
Synchronous pulse
Synchronous pulse
L/R
Bit Delay
SYNCDL bit
No
Control Data
Slot position
Secondary FS
Slot position
Not supported
Rev. 1.00 Sep. 19, 2007 Page 641 of 1136
REJ09B0359-0100