SH7730 Datasheet, PDF (602/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 18 Timer Unit (TMU)
Initial
Bit
Bit Name Value R/W Description
2 to 0 TPSC[2:0] 000
R/W Timer Prescaler 2, 1, and 0
Select the TCNT count clock.
000: Count on Pφ/4
001: Count on Pφ/16
010: Count on Pφ/64
011: Count on Pφ/256
100: Count on Pφ/1024
Others: Setting prohibited
Note: * Only 0 can be written to clear the flag.
18.2.3 Timer Constant Registers (TCOR)
TCOR are 32-bit readable/writable registers that specify the value to be set in TCNT when TCNT
underflows.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCOR
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCOR
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Sep. 19, 2007 Page 554 of 1136
REJ09B0359-0100