SH7730 Datasheet, PDF (526/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
14.4.2 Sleep Mode
(1) Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of the CPU registers remain unchanged. The on-chip peripheral
modules continue to operate in sleep mode and the clock continues to be output to the CKO pin.
The procedure for a transition to sleep mode is as follows:
1. Clear the STBY bit in STBCR to 0.
2. Execute the SLEEP instruction.
(2) Exit from Sleep Mode
Exit from sleep mode is driven by an interrupt (NMI, IRQ, or on-chip peripheral module) or a
reset.
Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, place the SPC
and SSR on the stack before executing the SLEEP instruction.
(a) Exit Driven by an Interrupt
Exit from sleep mode is triggered by an NMI, IRQ, or on-chip peripheral module interrupt. After
the interrupt, interrupt exception handling is executed and a code indicating the interrupt source is
set in INTEVT.
(b) Exit Driven by a Reset
Exit from sleep mode is triggered by a power-on reset.
Rev. 1.00 Sep. 19, 2007 Page 478 of 1136
REJ09B0359-0100