SH7730 Datasheet, PDF (756/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 22.16 Sample Flowchart for Receiving Serial Data (2)
In serial reception, the SCIF operates as described below.
1. The SCIF starts the reception in synchronization with the serial clock output.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed
(overrun error is detected), further reception is prevented.
3. After setting RDF to 1, if the receive FIFO data full interrupt enable bit (RIE) is set to 1 in
SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and
the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE)
in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
Figure 22.17 shows an example of SCIF receive operation.
Serial clock
Serial data
LSB
Bit 7 Bit 0
MSB
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
RDF
ORER
RXI
Data read from SCFRDR and
interrupt ^{RDF flag cleared to 0 by RXI}
request ^{interrupt handler}
One frame
RXI
interrupt
request
BRI interrupt request
by overrun error
Figure 22.17 Example of SCIF Receive Operation
Rev. 1.00 Sep. 19, 2007 Page 708 of 1136
REJ09B0359-0100