SH7730 Datasheet, PDF (510/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 13 Clock Pulse Generator (CPG)
13.6 Procedure for Ensuring the Internal Oscillator Settling Time on Exit
from Software Standby Mode
When the clock source is the crystal resonator and this is stopped in software standby mode,
OSCWTCR controls the crystal oscillation settling time when an NMI interrupt triggers exit from
software standby mode. The procedure is as follows.
1. Set the TIME bit and EXOEN bit of OSCWTCR to 1 before transition to software standby
mode.
2. In OSCWTCR, set the clock to be used in the CKS[2:0] bit field and the initial value of the
counter in the CNT [7:0] bit field. The values must be such that the counter takes longer to
overflow than the clock oscillation settling time.
3. After the STBY bit of STBCR has been set to 1, issuing a SLEEP instruction initiates entry to
software standby mode and stops the clock.
4. The watch timer counter (bits CNT[7:0] of OSCWTCR) starts counting on detection of an
edge of the NMI signal. When the CNT[7:0] counter overflows, the CPG starts the clock
supply and operation of this LSI restarts. At this point, the CNT[7:0] value stops at the set
initial value.
Rev. 1.00 Sep. 19, 2007 Page 462 of 1136
REJ09B0359-0100