SH7730 Datasheet, PDF (462/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Bit
29, 28
Initial
Bit Name Value
—
All 0
27 to 25 RPT[2:0] 000
22
—
0
23
DO
0
R/W
R
R/W
R
R/W
Descriptions
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Setting Renewal Specify
These bits are enabled in CHCR_0 to CHCR_3.
000: Normal mode (DMAC operation)
001: Repeat mode
SAR/DAR/TCR used as repeat area
010: Repeat mode
DAR/TCR used as repeat area
011: Repeat mode
SAR/TCR used as repeat mode
100: Reserved (setting prohibited)
101: Reload mode
SAR/DAR/TCR used as reload area
110: Reload mode
DAR/TCR used as reload area
111: Reload mode
SAR/TCR used as reload area
Reserved
This bit is always read as 0. The write value should
always be 0.
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR_0 and
CHCR_1.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
Rev. 1.00 Sep. 19, 2007 Page 414 of 1136
REJ09B0359-0100