SH7730 Datasheet, PDF (354/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
20
BAS
0
R/W
19

0
R
18 to 16 WW[2:0] 000
R/W
15 to 13 
All 0 R
12, 11 SW[1:0] 00
R/W
Description
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn and RDWR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read/write timing and
asserts the RDWR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RDWR signal at the write
timing.
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Wait Cycles in Write Access
Specify the number of wait cycles necessary for write
access.
000: Same number of cycles set by WR[3:0] (read
access wait)
001: 0 cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address/CSn Assertion to
RD/WEn Assertion
Specify the number of delay cycles from address and
CSn assertion to RD or WEn assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 1.00 Sep. 19, 2007 Page 306 of 1136
REJ09B0359-0100