SH7730 Datasheet, PDF (520/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
14
MSTP014 0
R/W Module Stop Bit 014
Setting this bit to 1 halts supply of the clock signal to
the CMT.
0: CMT operates
1: Clock supply to CMT halted
13
MSTP013 0
R/W Module Stop Bit 013
Setting this bit to 1 halts supply of the clock signal to
the RWDT.
0: RWDT operates
1: Clock supply to RWDT halted
12

1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
11, 10 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
MSTP009 0
R/W Module Stop Bit 009
Setting this bit to 1 halts supply of the clock signal to
the SCIF4 (SCIFA).
0: SCIF4 (SCIFA) operates
1: Clock supply to SCIF4 (SCIFA) halted
8
MSTP008 0
R/W Module Stop Bit 008
Setting this bit to 1 halts supply of the clock signal to
the SCIF5 (SCIFA).
0: SCIF5 (SCIFA) operates
1: Clock supply to SCIF5 (SCIFA) halted
7
MSTP007 0
R/W Module Stop Bit 007
Setting this bit to 1 halts supply of the clock signal to
the SCIF0.
0: SCIF0 operates
1: Clock supply to SCIF0 halted
Rev. 1.00 Sep. 19, 2007 Page 472 of 1136
REJ09B0359-0100