SH7730 Datasheet, PDF (452/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Figure 12.1 shows the block diagram of the DMAC.
On-chip
memory
On-chip
peripheral
module
Peripheral
bus controller
DMA transfer request signal
DMA transfer acknowledge signal
DEIm
Interrupt controller DADERR
Iteratiaon
control
Register
control
Start-up
control
Request
priority
control
SARm
DARm
TCRm
CHCRm
DMAOR
DMARS0 to
DMARS2
SARBn
DARBn
External ROM
External RAM
External I/O
(memory mapped)
External I/O
(with acknowledge-
ment )
DREQ0, DREQ1
DACK0, DACK1
TEND0, TEND1
Bus
interface
TCRBn
Bus state
controller
[Legend]
SARm:
SARBn:
DARm:
DARBn:
TCRm:
TCRBn:
CHCRm:
DMAOR:
DMA source address register
DMA source address register B
DMA destination address register
DMA destination address register B
DMA transfer count register
DMA transfer count register B
DMA channel control register
DMA operation register
DMARS0 to
DMARS2: DMA extended resource selectors 0 to 2
DEIm:
DMA transfer end/half-end interrupt request*
DADERR: ^{Address error interrupt request}
m:
0, 1, 2, 3, 4, 5
n:
0, 1, 2, 3
Note: * The half-end interrupt request is available
in channels 0 to 3.
Figure 12.1 Block Diagram of DMAC
Rev. 1.00 Sep. 19, 2007 Page 404 of 1136
REJ09B0359-0100