SH7730 Datasheet, PDF (496/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
12.5 Usage Notes
Pay attentions to the following notes when the DMAC is used.
12.5.1 DMA Transfer for Peripheral Modules
When executing a 16-byte DMA transfer for peripheral modules, set the TS[3:0] bits in CHCR to
B'1011 and execute in 16-byte 2-division transfer mode. This DMA transfer can only be executed
when a 16-byte boundary can be set in SAR or DAR as a transfer source address or transfer
destination address. When a transfer source address or transfer destination address is not a 16-byte
boundary, data cannot be transferred successfully.
12.5.2 Module Stop
While DMAC is in operation, the DMAC should not be stopped by the module stop register
(MSTPCR0). When modules are stopped, transfer contents cannot be guaranteed.
12.5.3 Address Error
When a DMA address error is occurred, set registers of all channels again and then start a transfer.
12.5.4 Notes on Burst Mode Transfer
During a burst mode transfer, following operation should not be executed until the transfer of
corresponding channel has completed.
1. Frequency should not be changed.
2. Transition to sleep mode should not be made.
3. Transition to standby mode should not be made.
Rev. 1.00 Sep. 19, 2007 Page 448 of 1136
REJ09B0359-0100