SH7730 Datasheet, PDF (523/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: When writing to a certain bit in MSTPCR1, read all values in MSTPCR1 first and rewrite the
certain bit, then return the renewed values back to MSTPCR1.
14.3.4 Module Stop Register 2 (MSTPCR2)
MSTPCR2 is a 32-bit readable/writable register that can individually start or stop the module
assigned to each bit.
MSTPCR2 can be accessed only in longwords.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
MSTP2 MSTP2 MSTP2 MSTP2
27
26
25
24
—
—
MSTP2 MSTP2
21
20
—
—
—
MSTP2
16
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R R R R R/W R/W R/W R/W R R R/W R/W R R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————— ——— ————————
Initial value: ₁
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
31 to 28 
All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
27
MSTP227 1
R/W Module Stop Bit 227
Clearing this bit to 0 starts supply of the clock signal to
the ADC.
0: ADC operates
1: Clock supply to ADC halted
26
MSTP226 1
R/W Module Stop Bit 226
Clearing this bit to 0 starts supply of the clock signal to
the DAC.
0: DAC operates
1: Clock supply to DAC halted
Rev. 1.00 Sep. 19, 2007 Page 475 of 1136
REJ09B0359-0100