SH7730 Datasheet, PDF (159/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 5 Exception Handling
(4) Data TLB Protection Violation Exception
• Source: The access does not accord with the UTLB protection information (PR bits or EPR
bits) shown in table 5.4 and table 5.5.
Table 5.4 UTLB Protection Information (TLB Compatible Mode)
PR
Privileged Mode
User Mode
00
Only read access possible
Access not possible
01
Read/write access possible
Access not possible
10
Only read access possible
Only read access possible
11
Read/write access possible
Read/write access possible
Table 5.5 UTLB Protection Information (TLB Extended Mode)
EPR [5]
0
1
Read Permission in Privileged Mode
Read access possible
Read access not possible
EPR [4]
0
1
Write Permission in Privileged Mode
Write access possible
Write access not possible
EPR [2]
0
1
Read Permission in User Mode
Read access possible
Read access not possible
EPR [1]
0
1
Write Permission in User Mode
Write access possible
Write access not possible
• Transition address: VBR + H'00000100
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
Rev. 1.00 Sep. 19, 2007 Page 111 of 1136
REJ09B0359-0100