SH7730 Datasheet, PDF (298/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
7
IRLM
0
R/W IRL Pin Mode
Selects whether IRQ3/IRL3 to IRQ0/IRL0 are used as
four independent interrupts (IRQ3 to IRQ0) or as 15-
level encoded interrupt requests (levels of IRL3 to IRL0
are encoded as H'F to H'1).
0: Used as pins for 15-level encoded interrupts, i.e.IRL3
to IRL0.
1: Used as pins for 4 independent interrupt requests,
i.e. IRQ3 to IRQ0.
6
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
5
LSH
0
R/W Holding function in level detection
In level-detection of the IRQ, IRL or PINT interrupts,
selects whether or not the interrupt requests are held by
the detection circuit.
0: Held
1: Not held
When the IRQ interrupt are in use with level sensing
and when IRL or PINT interrupts are in use, ordinarily
set the LSH bit to 1.
Setting the LSH bit to 0 means that even if the external
interrupt signal is negated, generation of the interrupt
will still indicated within the LSI.
4 to 0 —
All 0 —
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * This bit is set to 1 when the NMI input is at the high level and cleared to 0 when it is at
the low level.
Rev. 1.00 Sep. 19, 2007 Page 250 of 1136
REJ09B0359-0100