SH7730 Datasheet, PDF (725/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
22.3.7 Serial Status Register (SCFSR)
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive
FIFO data register (SCFRDR), and the lower 8 bits indicate the states of SCIF operation.
The CPU can always read the upper 8 bits of SCFSR and always read and write from/to the lower
8 bits. However, it cannot write 1 to the flags ER, TEND, TDFE, BRK, RDF, and DR. These flags
can be cleared to 0 only after 1 has been read from them. The PER flag and FER flag are read-only
and cannot be written to.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PERC[3:0]
FERC[3:0]
ER TEND TDFE BRK FER PER RDF DR
Initial value: 0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
R/W: R R R R R R R R R/W* R/W* R/W* R/W* R R R/W* R/W*
Bit
Bit Name
15 to 12 PERC[3:0]
Initial
Value
0000
11 to 8 FERC[3:0] 0000
R/W
R
R
Description
Number of Parity Errors
Indicate the number of data bytes including a parity
error in the receive data stored in the receive FIFO
data register (SCFRDR). After the ER bit in SCFSR is
set, the value in PERC[3:0] indicates the number of
parity errors in SCFRDR. When parity errors have
been found in all bytes in the 16 bytes of receive data
in SCFRDR, PERC[3:0] shows 0000.
Number of Framing Errors
Indicate the number of data bytes including a framing
error in the receive data stored in SCFRDR. After the
ER bit in SCFSR is set, the value in FERC[3:0]
indicates the number of framing errors in SCFRDR.
When framing errors have been found in all bytes in
the 16 bytes of receive data in SCFRDR, FERC[3:0]
shows 0000.
Rev. 1.00 Sep. 19, 2007 Page 677 of 1136
REJ09B0359-0100