SH7730 Datasheet, PDF (290/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 9 On-Chip Memory
9.5 Usage Notes
9.5.1 Page Conflict
In the event of simultaneous access to the same page from different buses, page conflict occurs.
Although each access is completed correctly, this kind of conflict tends to lower On-chip memory
accessibility. Therefore it is advisable to provide all possible preventative software measures. For
example, conflicts will not occur if each bus accesses different pages.
9.5.2 Access Across Different Pages
Access from the instruction bus is performed in one cycle when the access is made successively to
the same page but takes multiple cycles (a maximum of two wait cycles may be required) when
the access is made across pages or the previous access was made to memory other than IL
memory. For this reason, from the viewpoint of performance optimization, it is recommended to
design the software such that the target page does not change so often in access from the
instruction bus. For example, allocating a separate program for each page will deliver better
efficiency.
9.5.3 On-Chip Memory Coherency
In order to allocate instructions in the IL memory, write an instruction to the IL memory, execute
the following sequence, then branch to the rewritten instruction.
• SYNCO
• ICBI @Rn
In this case, the target for the ICBI instruction can be any address (IL memory address may be
possible) within the range where no address error exception occurs, and cache hit/miss is possible.
9.5.4 Sleep Mode
The SuperHyway bus master module, such as DMAC, cannot access OL memory and IL memory
in sleep mode.
Rev. 1.00 Sep. 19, 2007 Page 242 of 1136
REJ09B0359-0100