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SH7730 Datasheet, PDF (640/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series | |||
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Section 20 I2C Bus Interface (IIC)
20.4 Operation
20.4.1 I2C Bus Format
Figure 20.3 shows the I2C bus formats. Figure 20.4 shows the I2C bus timing. The first frame
following a start condition always consists of eight bits.
(a) I2C bus format (FS = 0)
S
SLA
R/W A
1
7
11
1
DATA
n
A
1
m
A/A P
11
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ⥠1)
(b) I2C bus format (Start condition retransmission, FS = 0)
S
SLA
R/W A
DATA
A/A S
1
7
11
n1
11
1
m1
SLA
R/W A
7
11
1
DATA
n2
m2
A/A P
11
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ⥠1)
Figure 20.3 I2C Bus Formats
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
SLA
R/W A
DATA
A
DATA
A
P
Figure 20.4 I2C Bus Timing
[Legend]
S:
Start condition. The master device drives SDA from high to low while SCL is high.
SLA: Slave address
R/W: Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P:
Stop condition. The master device drives SDA from low to high while SCL is high.
Rev. 1.00 Sep. 19, 2007 Page 592 of 1136
REJ09B0359-0100
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