SH7730 Datasheet, PDF (656/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 20 I2C Bus Interface (IIC)
20.7 Usage Notes
20.7.1 Restriction on the Setting of Transfer Rate in Multi-Master Operation
When the IIC transfer rate of this LSI is set slower than that of other masters in multi-master
operation, the SCL may be output with an unexpected width. To avoid this, set the transfer rate to
at least 1/1.8 of the fastest rate among the other masters. For example, when the fastest transfer
rate of the other masters is 400 Kbps, the IIC transfer rate of this LSI must be set to at least 223
Kbps (=400/1.8).
20.7.2 Restriction on the Use of Bit-Operation Instructions to Set MST and TRS in Multi-
Master Operation
When the MST and the TRS are set for master transfer in multi-master operation, a contradictory
event where AL=1 in ICSR and the mode is master transmission (MST=1, TRS=1) may occur, if
arbitration lost signal is generated during execution of the bit operation instruction to set TRS.
Avoid this in the following way:
1. In multi-master operation, use an MOV instruction to set MST and TRS.
2. When arbitration is lost, ensure that MST = 0 and TRS = 0. If the values are other than MST =
0 and TRS = 0, set the MST and the TRS bits to 0.
Rev. 1.00 Sep. 19, 2007 Page 608 of 1136
REJ09B0359-0100