SH7730 Datasheet, PDF (788/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
4. When sampling rate is 1/13
Error (%) =
Pφ × 10⁶
- 1 × 100
(1+N) × B × 26 × 2^2n-1
5. When sampling rate is 1/27
Error (%) =
Pφ × 10⁶
- 1 × 100
(1+N) × B × 54 × 2^2n-1
23.3.10 FIFO Control Register (SCAFCR)
SCAFCR is a 16-bit readable/writable register that resets the number of data bytes in the transmit
and receive FIFO registers, sets the number of trigger data, and contains an enable bit for the loop
back test.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TSE
TCR
ST
—
—
—
RSTRG[2:0]
RTRG[1:0]
TTRG[1:0]
MCE
TFR
ST
RFR
ST
LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15
TSE
0
R/W Transmit Data Stop Enable
Enables or disables transmit data stop function. This
function is enabled only in asynchronous mode. Since
this function is not supported in synchronous mode,
clear this bit to 0 in synchronous mode.
0: Transmit data stop function disabled
1: Transmit data stop function enabled
14
TCRST
0
R/W Transmit Count Reset
Clears the transmit count to 0. This bit is available
while the transmit data stop function is enabled.
0: Transmit count reset disabled*
1: Transmit count reset enabled (cleared to 0)
Note: * The transmit count is reset (cleared to 0) by
a power-on reset or manual reset.
Rev. 1.00 Sep. 19, 2007 Page 740 of 1136
REJ09B0359-0100