SH7730 Datasheet, PDF (433/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
CKO
T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2
A25 to A5
A4 to A0
CS
RDWR
RD
D31 to D0
WAIT
BS
DACK
Figure 11.31 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits,
16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2,
Access Wait for 2nd Time and after = 1)
11.5.7 Byte-Selection SRAM Interface
The byte-selection SRAM interface is for access to an SRAM which has a byte-selection pin
(WEn). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte
selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byte-
selection SRAM interface is the same as that for the normal space interface. While in read access
of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin, which is
different from that for the normal space interface. The basic access timing is shown in figure
11.32. In write access, data is written to the memory according to the timing of the byte-selection
pin (WEn). For details, refer to the data sheet for the corresponding memory.
Rev. 1.00 Sep. 19, 2007 Page 385 of 1136
REJ09B0359-0100