SH7730 Datasheet, PDF (493/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
12.4.7 DREQ Pin Sampling Timing
Figures 12.12 to 12.15 show the sample timing of the DREQ input in each bus mode, respectively.
CKO
Bus cycle
DREQ
(Rising edge)
CPU
CPU
1st acceptance
DMAC
CPU
2nd acceptance
CPU
DACK
(High-active)
Acceptance
started
: Non-sensitive
period
Figure 12.12 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CKO
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(High-active)
CPU
CPU
1st acceptance
DMAC
CPU
CPU
2nd acceptance
Acceptance started
CKO
Bus cycle
DREQ
(Overrun 1,
high-level)
DACK
(High-active)
CPU
CPU
1st acceptance
DMAC
CPU
2nd acceptance
CPU
Acceptance started
: Non-sensitive
period
Figure 12.13 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Rev. 1.00 Sep. 19, 2007 Page 445 of 1136
REJ09B0359-0100