SH7730 Datasheet, PDF (357/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
19

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
18 to 16 WW[2:0] 000
R/W Number of Wait Cycles in Write Access
Specify the number of wait cycles necessary for write
access.
000: Same number of cycles set by WR[3:0] (read
access wait)
001: 0 cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 
All 0
12, 11 SW[1:0] 00
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Number of Delay Cycles from Address/CSn Assertion to
RD/WEn Assertion
Specify the number of delay cycles from address and
CSn assertion to RD or WEn assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 1.00 Sep. 19, 2007 Page 309 of 1136
REJ09B0359-0100