SH7730 Datasheet, PDF (154/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 5 Exception Handling
5.6 Description of Exceptions
The various exception handling operations explained here are exception sources, transition address
on the occurrence of exception, and processor operation when a transition is made.
5.6.1 Resets
(1) Power-On Reset
• Condition:
Power-on reset request
• Operations:
Exception code H'000 is set in EXPEVT, initialization of the CPU and on-chip peripheral
module is carried out, and then a branch is made to the reset vector (H'A0000000). For details,
see the section 14, Reset and Power-Down Modes, and the register descriptions in the relevant
sections. A power-on reset should be executed when power is supplied.
(2) Manual Reset
• Condition:
Manual reset request
• Operations:
Exception code H'020 is set in EXPEVT, initialization of the CPU and on-chip peripheral
module is carried out, and then a branch is made to the branch vector (H'A0000000). The
registers initialized by a power-on reset and manual reset are different. For details, see the
section 14, Reset and Power-Down Modes, and the register descriptions in the relevant
sections. In cases where the register descriptions in the relevant sections do not include the
descriptions of manual reset, the same states as those of the power-on reset are applied.
(3) H-UDI Reset
• Source: SDIR.TI[7:4] = B'0110 (negation) or B'0111 (assertion)
• Transition address: H'A0000000
• Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A0000000.
CPU and on-chip peripheral module initialization is performed. For details, see section 31,
User Debugging Interface (H-UDI), and the register descriptions in the relevant sections.
Rev. 1.00 Sep. 19, 2007 Page 106 of 1136
REJ09B0359-0100