SH7730 Datasheet, PDF (286/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 9 On-Chip Memory
9.2 Register Descriptions
The following register is related to the on-chip memory.
Table 9.2 Register Configuration
Name
Area 7
Abbreviation R/W P4 Address* Address*
Access Size
On-chip memory control
register
RAMCR
R/W H'FF00 0074 H'1F00 0074 32
Note: * The P4 address is the address used when using P4 area in the virtual address space.
The area 7 address is the address used when accessing from area 7 in the physical
address space using the TLB.
Table 9.3 Register States in Each Processing Mode
Name
Abbreviation
On-chip memory control register RAMCR
Power-On Reset Sleep
Standby
H'0000 0000
Retained Retained
9.2.1 On-Chip Memory Control Register (RAMCR)
RAMCR controls the protective functions in the on-chip memory.
When updating RAMCR, please follow limitation described at section 8.2.4, On-Chip Memory
Control Register (RAMCR).
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMD RP IC2W OC2W ICWPD
Initial value : 0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R R R R R
Bit
Bit Name
31to10 —
Initial
Value
All 0
R/W Description
R
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
Rev. 1.00 Sep. 19, 2007 Page 238 of 1136
REJ09B0359-0100