SH7730 Datasheet, PDF (774/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
23.3.6 Serial Control Register (SCASCR)
SCASCR is a 16-bit readable/writable register that operates the SCI transmitter/receiver,
enables/disables interrupt requests, and selects the transmit/receive clock source.
Bit: 15 14 13
TDR RDR
QE QE
—
Initial value: 0
0
0
R/W: R/W R/W R
12 11 10 9
8
7
6
5
4
3
— TSIE ERIE BRIE DRIE TIE RIE TE RE —
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R
2
1
0
— CKE[1:0]
0
0
0
R R/W R/W
Bit
Bit Name
15
TDRQE
14
RDRQE
13,12 
11
TSIE
Initial
Value
0
0
All 0
0
R/W Description
R/W Transmit Data Transfer Request Enable
Selects whether to issue the transmit-FIFO-data-empty
interrupt request or DMA transfer request when TIE = 1
and transmit FIFO empty interrupt is generated at the
transmission.
0: Interrupt request is issued to CPU
1: Transmit data transfer request is issued to DMAC
R/W Receive Data Transfer Request Enable
Selects whether to issue the receive-FIFO-data-full
interrupt or DMA transfer request when RIE = 1 and
receive FIFO data full interrupt is generated at the
reception.
0: Interrupt request is issued to CPU
1: Receive data transfer request is issued to DMAC
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Transmit Data Stop Interrupt Enable
Enables or disables the generation of the transmit-
data-stop interrupt requested when the TSE bit in
SCAFCR is enabled and the TSF flag in SCASSR is
set to 1.
0: The transmit-data-stop-interrupt disabled*
1: The transmit-data-stop-interrupt enabled
Note: * The transmit data stop interrupt request is
cleared by reading the TSF flag after it has
been set to 1, then clearing the flag to 0, or
clearing the TSIE bit to 0.
Rev. 1.00 Sep. 19, 2007 Page 726 of 1136
REJ09B0359-0100