SH7730 Datasheet, PDF (855/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 24 IrDA Interface (IrDA)
(3) Internal Clock Generation for Transmit and Receive Pulse Modulation and
Demodulation
The 1.8432-MHz clock used in the transmit and receive pulse modulator/demodulator block is
generated by the following equation.
System clock (SCLK) [Hz]
1.8432-MHz clock = _{IRBCA + ( IRBC + 1)}
IRBC: Baud rate counter value for infrared transmit and receive pulse modulation
and demodulation (value specified in the IRBC3 to IRBC0 bits in IRIF_SIR2)
IRBCA: Baud rate error correction value for infrared transmit and receive pulse
modulation and demodulation (value selected with the IRBCA3 to IRBCA0
bits in IRIF_SIR1)
The 1.8432-MHz clock is used to measure 1.63 µs and is necessary in the following operations.
• Generating a 1.63-µs infrared transmit (light-emit) pulse
• Recognizing an infrared receive (light-receive) pulse
• Detecting an error in the width (shorter than the standard) of an infrared receive (light-receive)
pulse
The clock shown in the above equation is the clock input to the controller. Every time the integer
part of the baud rate count is reloaded, the fraction part selected by the baud rate error correction
register is accumulated. When an overflow occurs during fraction part accumulation, 1 is added to
the integer part and the resultant value is reloaded to the counter. This means that the error in the
baud rate count is eliminated by adding 1 to the count when the accumulated error in the fraction
part reaches 1.
(4) Notes on Infrared Transmit and Receive Pulse Modulation and Demodulation
(a) Errors in the width of infrared receive (light-receive) pulses
The infrared receive pulse error flag (IRERR) is set to 1 when the width of an infrared receive
(light-receive) pulse is determined as outside of the standard; that is, in the following cases.
• When a low level of an infrared receive pulse is detected for only one cycle of the 1.8432-MHz
clock (shorter than the standard)
• When a low level of an infrared receive pulse is detected for five or more continuous cycles of
the MSFCLK_IN clock (longer than the standard)
• When a high level of an infrared receive pulse is detected for only one cycle of the 1.8432-
MHz clock (lacking a pulse)
Rev. 1.00 Sep. 19, 2007 Page 807 of 1136
REJ09B0359-0100