SH7730 Datasheet, PDF (609/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 19 Compare Match Timer (CMT)
Section 19 Compare Match Timer (CMT)
This LSI includes 5 channels (channels 0 to 4) of 32-bit compare match timers (CMT).
19.1 Features
• 16 bits/32 bits can be selected.
• Provided with an auto-reload up counter.
• Provided with 32-bit constant registers and 32-bit up counters that can be written or read at any
time.
• For each of channels 0 to 4, the counter-input clock is selectable from among 3 signals.
 Peripheral clock (Pφ): 1/8, 1/32, and 1/128
• One-shot operation and free-running operation are selectable.
• Allows selection of compare match or overflow for the interrupt source.
• Issuing of DMA transfer requests on compare match or overflow of the counter is selectable on
channels 0 to 4.
• Module standby mode can be set.
Rev. 1.00 Sep. 19, 2007 Page 561 of 1136
REJ09B0359-0100