SH7730 Datasheet, PDF (415/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 11.19 or 9.22, followed by repetition of the cycle in figure 11.20 or 9.23. An access
to a different area during this time has no effect. If there is an access to a different row address in
the bank active state, after this is detected the bus cycle in figure 11.21 or 9.24 is executed instead
of that in figure 11.20 or 9.23. In bank active mode, too, all banks become inactive after a refresh
cycle or after the bus is released as the result of bus arbitration.
CKO
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RDWR
DQMxx
D31 to D0
BS
DACKn*²
Td1
Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 11.19 Burst Read Timing (No Auto-Precharge)
Rev. 1.00 Sep. 19, 2007 Page 367 of 1136
REJ09B0359-0100