SH7730 Datasheet, PDF (1031/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
Bit
Bit Name
23 to 16 AIV
15
DBE
14 to 12 SZ
11
ETBE
10 to 8 —
Initial
Value
All 0
0
All 0
0
All 0
R/W Description
R/W ASID Specify
Specifies the ASID value to be included in the match
conditions.
R/W Data Value Enable*³
Specifies whether or not to include the data value in the
match condition. This bit is valid only when the
operand access cycle is specified as a match condition.
0: The data value is not included in the match
conditions; thus, not checked.
1: The data value is included in the match conditions.
R/W Operand Size Select
Specifies the operand size to be included in the match
conditions. This bit is valid only when the operand
access cycle is specified as a match condition.
000: The operand size is not included in the match
condition; thus, not checked (any operand size
specifies the match condition). *¹
001: Byte access
010: Word access
011: Longword access
100: Quadword access*²
Others: Reserved (setting prohibited)
R/W Execution Count Value Enable
Specifies whether or not to include the execution count
value in the match conditions. If this bit is 1 and the
match condition satisfaction count matches the value
specified by the CETR1 register, the operation
specified by the CRR1 register is performed.
0: The execution count value is not included in the
match conditions; thus, not checked.
1: The execution count value is included in the match
conditions.
R Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
Rev. 1.00 Sep. 19, 2007 Page 983 of 1136
REJ09B0359-0100