SH7730 Datasheet, PDF (113/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 3 Instruction Set
Instruction
Operation
Instruction Code
STC
VBR,Rn
VBR → Rn
0000nnnn00100010
STC
SSR,Rn
SSR → Rn
0000nnnn00110010
STC
SPC,Rn
SPC → Rn
0000nnnn01000010
STC
SGR,Rn
SGR → Rn
0000nnnn00111010
STC
DBR,Rn
DBR → Rn
0000nnnn11111010
STC
Rm_BANK,Rn Rm_BANK → Rn
(m = 0 to 7)
0000nnnn1mmm0010
STC.L
SR,@-Rn
Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011
STC.L
GBR,@-Rn
Rn – 4 → Rn, GBR →
(Rn)
0100nnnn00010011
STC.L
VBR,@-Rn
Rn – 4 → Rn, VBR →
(Rn)
0100nnnn00100011
STC.L
SSR,@-Rn
Rn – 4 → Rn, SSR →
(Rn)
0100nnnn00110011
STC.L
SPC,@-Rn
Rn – 4 → Rn, SPC →
(Rn)
0100nnnn01000011
STC.L
SGR,@-Rn
Rn – 4 → Rn, SGR →
(Rn)
0100nnnn00110010
STC.L
DBR,@-Rn
Rn – 4 → Rn, DBR →
(Rn)
0100nnnn11110010
STC.L
Rm_BANK,@- Rn – 4 → Rn,
Rn
Rm_BANK → (Rn)
(m = 0 to 7)
0100nnnn1mmm0011
STS
MACH,Rn
MACH → Rn
0000nnnn00001010
STS
MACL,Rn
MACL → Rn
0000nnnn00011010
STS
PR,Rn
PR → Rn
0000nnnn00101010
STS.L
MACH,@-Rn Rn – 4 → Rn, MACH → 0100nnnn00000010
(Rn)
STS.L
MACL,@-Rn Rn – 4 → Rn, MACL → 0100nnnn00010010
(Rn)
STS.L
PR,@-Rn
Rn – 4 → Rn, PR → (Rn) 0100nnnn00100010
SYNCO
Data accesses invoked
by the following
instructions are not
executed until execution
of data accesses which
precede this instruction
has been completed.
0000000010101011
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Rev. 1.00 Sep. 19, 2007 Page 65 of 1136
REJ09B0359-0100