SH7730 Datasheet, PDF (880/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 25 SIM Card Module (SIM)
Initial
Bit
Bit Name Value R/W Description
6
LCB
0
R/W Last Character
When this bit is set to 1, the character protection time is
2 etu, and the setting of the guard extension register is
invalid.
0: Character protection time is determined by the value
of the guard extension register
1: Character protection time is 2 etu
5
PB
0
R/W Protocol
Selects the T = 0 or T = 1 protocol.
0: Smart card interface operates according to the T = 0
protocol
1: Smart card interface operates according to the T = 1
protocol
4
WECC
0
R/W Wait Error Counter Clear
Enables or disables clearing of the wait error counter.
0: Wait error counter is not cleared and wait errors are
detected (initial value)
1: Wait error counter is cleared and wait errors are not
detected
3
SDIR
0
R/W Smart Card Data Transfer Direction
Selects the format for serial/parallel conversion.
0: Transmits the SCTDR contents in LSB-first.
Received data is stored in SCRDR as LSB-first.
1: Transmits the SCTDR contents in MSB-first.
Received data is stored in SCRDR as MSB-first.
2
SINV
0
R/W Smart Card Data Inversion
Specifies inversion of the data logic level. In
combination with the function of bit 3, used for
transmission to or reception from the inverse
convention card. The SINV bit does not affect the parity
bit.
0: Transmits the SCTDR contents without change.
Stores received data in SCRDR without change.
1: Inverts the SCTDR contents and transmits it.
Inverts received data and stores it in SCRDR.
Rev. 1.00 Sep. 19, 2007 Page 832 of 1136
REJ09B0359-0100