PXD10RM Datasheet, PDF (999/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

29.3.2.4 Power Domain Status Register (PCU_PSTAT)
Address 0xC3FE_8040
Access: Supervisor read
0
1
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R0
0
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W
Reset 0
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R
W
Reset 0
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1
1
1
Figure 29-5. Power Domain Status Register (PCU_PSTAT)
This register reflects the power status of all available power domains.
Table 29-4. Power Domain Status Register (PCU_PSTAT) Field Descriptions
Field
PDn Power status for power domain #n
0 Power domain is inoperable
1 Power domain is operable
Description
29.4 Functional Description
29.4.1 General
The MC_PCU controls all available power domains on a device mode basis. The PCU_PCONFn registers
specify during which system/user modes a power domain is powered up. The power state for each
individual power domain is reflected by the bits in the PCU_PSTAT register.
On a mode change, the MC_PCU evaluates which power domain(s) must change power state. The power
state is controlled by a state machine (FSM) for each individual power domain (see Figure 3-1) which
ensures a clean and safe state transition.
29.4.2 Reset / Power-On Reset
After any reset, the SoC will transition to the RESET mode during which all power domains are powered
up (see the MC_ME chapter). Once the reset sequence has been completed, the DRUN mode is entered
and software can begin the MC_PCU configuration.
29.4.3 MC_PCU Configuration
Per default, all power domains are powered in all modes other than STANDBY. Software can change the
configuration for each power domain on a mode basis by programming the PCU_PCONFn registers.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
29-7