PXD10RM Datasheet, PDF (938/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 25-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions (continued)
Field
SAFE
TEST
RESET
Peripheral control during SAFE
0 Peripheral is frozen with clock gated
1 Peripheral is active
Peripheral control during TEST
0 Peripheral is frozen with clock gated
1 Peripheral is active
Peripheral control during RESET
0 Peripheral is frozen with clock gated
1 Peripheral is active
Description
25.3.2.21 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
Address 0xC3FD_C0A0 - 0xC3FD_C0BC
Access: Supervisor read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-22. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
These registers configure eight different types of peripheral behavior during non-run modes.
Table 25-14. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions
Field
STANDBY
STOP
HALT
Peripheral control during STANDBY
0 Peripheral is frozen with clock gated
1 Peripheral is active
Peripheral control during STOP
0 Peripheral is frozen with clock gated
1 Peripheral is active
Peripheral control during HALT
0 Peripheral is frozen with clock gated
1 Peripheral is active
Description
25-32
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor