PXD10RM Datasheet, PDF (485/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Name
DAE
DOE
NCE
SGE
SBE
DBE
Table 15-3. DMA Error Status (DMAES) field descriptions (continued)
Description
Destination Address Error
Destination Offset Error
Nbytes/Citer Configuration Error
Scatter/Gather Configuration Error
Source Bus Error
Destination Bus Error
Value
0 No destination address configuration error.
1 The last recorded error was a configuration error
detected in the TCD.daddr field. TCD.daddr is
inconsistent with TCD.dsize.
0 No destination offset configuration error.
1 The last recorded error was a configuration error
detected in the TCD.doff field. TCD.doff is
inconsistent with TCD.dsize.
0 No nbytes/citer configuration error.
1 The last recorded error was a configuration error
detected in the TCD.nbytes or TCD.citer fields.
TCD.nbytes is not a multiple of TCD.ssize and
TCD.dsize, or TCD.citer is equal to zero, or
TCD.citer.e_link is not equal to TCD.biter.e_link.
0 No scatter/gather configuration error.
1 The last recorded error was a configuration error
detected in the TCD.dlast_sga field. This field is
checked at the beginning of a scatter/gather
operation after major loop completion if TCD.e_sg is
enabled. TCD.dlast_sga is not on a 32 byte
boundary.
0 No source bus error.
1 The last recorded error was a bus error on a source
read.
0 No destination bus error.
1 The last recorded error was a bus error on a
destination write.
15.2.1.3 DMA Enable Request (DMAERQH, DMAERQL)
The DMAERQ{H,L} registers provide a bit map for the implemented channels {16,32,64} to enable the
request signal for each channel. DMAERQH supports channels 63-32, while DMAEQRL covers channels
31-00. The state of any given channel enable is directly affected by writes to this register; it is also affected
by writes to the DMASERQ and DMACERQ registers. The DMA{S,C}ERQ registers are provided so that
the request enable for a single channel can easily be modified without the need to perform a
read-modify-write sequence to the DMAERQ{H,L} registers.
Both the DMA request input signal and this enable request flag must be asserted before a channel’s
hardware service request is accepted. The state of the DMA enable request flag does not affect a channel
service request made explicitly through software or a linked channel request. See Figure 15-4 and
Table 15-4 for the DMAERQ definition.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
15-15