PXD10RM Datasheet, PDF (1051/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

When the QuadSPI is the bus master, the CPOL and CPHA bits in the QuadSPI Clock and Transfer
Attributes Registers (QSPI_CTARx) select the polarity and phase of the serial clock, SCK. The polarity
bit selects the idle state of the SCK. The clock phase bit selects if the data on SO is valid before or on the
first SCK edge.
When the QuadSPI is the bus Slave, CPOL and CPHA bits in the QSPI_CTAR0 select the polarity and
phase of the serial clock. For SPI Slaves the QSPI_CTAR0 is used, and for DSI Slaves the QSPI_CTAR1
is used. Even though the bus Slave does not control the SCK signal, clock polarity, clock phase and number
of bits to transfer must be identical for the master device and the slave device to ensure proper
transmission.
The QuadSPI supports four different transfer formats:
• Classic SPI with CPHA=0
• Classic SPI with CPHA=1
• Modified Transfer format with CPHA = 0
• Modified Transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The QuadSPI can sample the incoming data later than halfway through the
cycle to give the peripheral more setup time. The MTFE bit in the QSPI_MCR selects between Classic SPI
Format and Modified Transfer Format. The Classic SPI Formats are described in Section 30.5.2.8.1,
Classic SPI Transfer Format (CPHA = 0),” and Section 30.5.2.8.2, Classic SPI Transfer Format (CPHA =
1).” The Modified Transfer Formats are described in Section 30.5.2.8.3, Modified SPI Transfer Format
(MTFE = 1, CPHA = 0),” and Section 30.5.2.8.4, Modified SPI Transfer Format (MTFE = 1, CPHA = 1).”
In SPI Master Mode and SPI Slave Mode the QuadSPI provides the option of keeping the PCS signals
asserted between frames. See Section 30.5.2.8.5, Continuous Selection Format,” for details.
30.5.2.8.1 Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in Figure 30-27 is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
SI pins on the odd-numbered SCK edges and change the data on their SO pins on the even-numbered SCK
edges.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-47