PXD10RM Datasheet, PDF (1215/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

37.5.3.13 Parallel GPIO Pad Data In Register (PGPDI0–PGPDI4)
These registers hold the synchronized input value from the pads.
Address: Base + 0x0C40 - 0x0C50 (5 registers)
0
1
2
3
4
5
6
7
8
9
R
PPDI[x][15:0]
W
Reset ₀
0
0
0
0
0
0
0
0
0
Access: User read
10
11
12
13
14
15
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PPDI[x+1][15:0]
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 37-16. Parallel GPIO Pad Data In Register (PGPDI0)
Table 37-16. PGPDI field descriptions
Field
PPDI[x]
Description
Parallel Pad Data In
Read the current pad value.
Accesses to this register location are coherent with accesses to the bit-wise GPIO Pad Data Input
Registers (GPDI0_3 - GPDI132_135).
The x and bit index define which PPDI register bit is equivalent to which PDI register bit according
to the following equation:
PPDI[x][y] = PDI[(x*16)+y]
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
37-21