PXD10RM Datasheet, PDF (326/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

11.8.7.4 Transmit FIFO Underflow Interrupt Request (TFUF)
The transmit FIFO underflow request indicates that an underflow condition in the TX FIFO has occurred.
The transmit underflow condition is detected only for DSPI modules operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in slave mode and SPI
configuration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while
the TFUF_RE bit in the DSPIx_RSER is set, an interrupt request is generated.
11.8.7.5 Receive FIFO Drain Interrupt or DMA Request (RFDF)
The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO drain request
is generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the
DSPIx_RSER is set. The RFDF_DIRS bit in the DSPIx_RSER selects whether a DMA request or an
interrupt request is generated.
11.8.7.6 Receive FIFO Overflow Interrupt Request (RFOF)
The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has occurred. A
receive FIFO overflow request is generated when RX FIFO and shift register are full and a transfer is
initiated. The RFOF_RE bit in the DSPIx_RSER must be set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the DSPIx_MCR, the data from the transfer that generated the
overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is
shifted in to the shift register. If the ROOE bit is negated, the incoming data is ignored.
11.8.7.7 FIFO Overrun Request (TFUF) or (RFOF)
The FIFO overrun request indicates that at least one of the FIFOs in the DSPI has exceeded its capacity.
The FIFO overrun request is generated by logically OR’ing together the RX FIFO overflow and TX FIFO
underflow signals.
11.8.8 Power Saving Features
The DSPI supports three power-saving strategies:
• External stop mode
• Module disable mode—clock gating of non-memory mapped logic
• Clock gating of slave interface signals and clock to memory-mapped logic
11.8.8.1 External Stop Mode
The DSPI supports the Stop Mode protocol. When a request is made to enter External Stop Mode, the DSPI
block acknowledges the request by negating ipg_stop_ack. When the DSPI is ready to have its clocks shut
off the ipg_stop_ack signal is asserted. If a serial transfer is in progress, the DSPI waits until it reaches the
frame boundary before it asserts ipg_stop_ack. While the clocks are shut off, the DSPI memory-mapped
logic is not accessible. The states of the interrupt and DMA request signals cannot be changed while in
External Stop Mode. Implementation of IPI Green Line Stop Mode in an SoC is optional.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor