PXD10RM Datasheet, PDF (1064/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

30.5.3.5 Serial Flash Mode Interrupt and DMA Requests
In Serial Flash Mode the QuadSPI has 8 different flags that can only generate interrupt requests and one
flag that can generate interrupt as well as DMA requests. Table 30-46 lists the eight conditions. Note that
the flags mentioned in the table relate to the Serial Flash Mode Flag Register (QSPI_SFMFR).
Table 30-46. Serial Flash Mode Interrupt and DMA Request Conditions
Condition
TX Buffer Fill
TX Buffer Underrun
RX Buffer Drain
RX Buffer Overflow
AHB Buffer Overflow
IP Command Trigger during AHB Access Error
IP Command Trigger during IP Access
Instruction Code Error
Transaction Finished
Flag
(QSPI_SPISR)
TBFF
TBUF
RBDF
RBOF
ABOF
IPAEF
IPIEF
ICEF
TFF
DMA
X
Each condition has a flag bit in the Serial Flash Mode Flag Register (QSPI_SFMFR) and a Request Enable
bit in the SFM Interrupt and DMA Request Select and Enable Register (QSPI_SFMRSER). The RX Buffer
Drain Flag (RBDF) has separate enable bits for generating IRQ and DMA requests. Note that not each
single flag is represented by an individual IRQ line.
30.5.3.5.1 Transmit Buffer Fill Interrupt Request
The Transmit Buffer Fill IRQ indicates that the TX Buffer can accept new data. It is asserted if the
QSPI_SFMFR[TBFF] flag is asserted and if the corresponding enable bit (QSIP_SFMRSER[TBFIE]) is
set. Refer to Section 30.5.3.6, TX Buffer Operation” for details about the assertion of the
QSPI_SFMFR[TBFF] flag.
30.5.3.5.2 Receive Buffer Drain Interrupt or DMA Request
The Receive Buffer Drain IRQ derived from the QSPI_SFMFR[RBDF] flag indicates that the RX Buffer
of the QuadSPI module has data available from the serial flash device to be read by the host. It remains set
as long as the RX Buffer is not empty. The QSPI_SFMRSER[RBDIE] bit enables the related IRQ.Aside
from the IRQ it is possible to handle RX Buffer drain by DMA. If the QSPI_SFMRSER[RBDDE] bit is
set each write of the module into the RX Buffer triggers a DMA request. The application must set the
environment appropriately (for example, the DMA controller) for the DMA transfers.
30.5.3.5.3 Buffer Overflow/Underrun Interrupt Request
The Buffer Overflow/Underrun IRQ is a combination of the following flags (all located in the
QSPI_SPIFR register with the related enable bits in the QSPI_SPIRSER register):
30-60
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor