PXD10RM Datasheet, PDF (850/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
IDPEF
22
FEF
23
BOF
24
25:30
NF
31
Table 23-9. LINESR field descriptions (continued)
Description
Identifier Parity Error Flag
This bit is set by hardware and indicates that a Identifier Parity error occurred.
Note: Header interrupt is triggered when SFEF or BDEF or IDPEF bit is set and HEIE bit in LINIER
is set.
Framing Error Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a framing error
(invalid stop bit). This error can occur during reception of any data in the response field (Master or
Slave mode) or during reception of Synch Field or Identifier Field in Slave mode.
Buffer Overrun Flag
This bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. If
RBLM in LINCR1 is set then the new byte received is discarded. If RBLM is reset then the new byte
overwrites the buffer. It can be cleared by software.
Reserved
Noise Flag
This bit is set by hardware when noise is detected on a received character. This bit is cleared by
software.
23.7.2.5 UART mode control register (UARTCR)
Address: Base + 0x0010
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
R0
W
Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0000
TDFL[0:1]
RDFL[0:1]
RXEN TXEN OP PCE WL UART
000000000000000
Figure 23-11. UART mode control register (UARTCR)
Table 23-10. UARTCR field descriptions
Field
0:16
TDFL[0:1]
17:18
Description
Reserved
Transmitter Data Field length
These bits set the number of bytes to be transmitted in UART mode. These bits can be
programmed only when the UART bit is set. TDFL[0:1] = Transmit buffer size – 1.
00 Transmit buffer size = 1.
01 Transmit buffer size = 2.
10 Transmit buffer size = 3.
11 Transmit buffer size = 4.
23-18
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor