PXD10RM Datasheet, PDF (1044/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• Module Disable Mode: The mode is used for power management. The clock to the non-memory
mapped logic in the QuadSPI can be stopped while in Module Disable Mode.The module enters
the mode by setting QSPI_MCR[MDIS] or when a request is asserted by an external controller
while QSPI_MCR[DOZE] is set. See Section 30.5.4.2, Module Disable Mode,” for more details.
30.5.2 SPI (Serial Peripheral Interface) Modes
In the SPI Master and SPI Slave Mode serial data are transferred using a shift register and a selection of
programmable transfer attributes. The SPI frames can be from four to sixteen bits long. The data to be
transmitted can come from queues stored in RAM external to the QuadSPI. Host software or a DMA
Controller can transfer the SPI data from the queues to a First-In First-Out (FIFO) buffer. The received
data is stored in entries in the RX FIFO. Host software or a DMA Controller transfer the received data from
the RX FIFO to memory external to the QuadSPI. The FIFO buffer operations are described in
Section 30.5.2.5, Transmit First In First Out (TX FIFO) Buffering Mechanism,” and Section 30.5.2.6,
Receive First In First Out (RX FIFO) Buffering Mechanism.” The interrupt and DMA request conditions
are described in Section 30.5.2.10, SPI Mode Interrupt and DMA Requests.”
There are two different SPI Modes: Master Mode and Slave Mode. The FIFO operations are similar for
the Master Mode and Slave Mode. The main difference is that in Master Mode the QuadSPI initiates and
controls the transfer according to the fields in the SPI Command field of the TX FIFO entry. In Slave Mode
the QuadSPI only responds to transfers initiated by a bus master external to the QuadSPI and the SPI
Command field of the TX FIFO entry is ignored.
The 16-bit shift register in the Master and the 16-bit shift register in the Slave are linked by the SO and SI
signals to form a distributed 32-bit register. When a data transfer operation is performed, data is serially
shifted a pre-determined number of bit positions. Because the registers are linked, data is exchanged
between the Master and the Slave; the data that was in the Master’s shift register is now in the shift register
of the Slave, and vice versa. At the end of a transfer, the TCF bit in the QSPI_SPISR is set to indicate a
completed transfer. Figure 30-23 illustrates how Master and Slave data is exchanged.
SPI Master
Shift Register
Baud Rate
Generator
SI
SO
SCK
PCSx
SO
SI
SCK
SPI Slave
Shift Register
SS
Figure 30-23. SPI Serial Protocol Overview
The QuadSPI has eight Peripheral Chip Select (PCS) signals that are used to select which of the Slaves to
communicate with.
30-40
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor