PXD10RM Datasheet, PDF (289/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

11.7.2 Register description
11.7.2.1 DSPI Module Configuration Register (DSPIx_MCR)
The DSPIx_MCR contains bits which configure attributes of the DSPI operation. The values of the HALT
and MDIS bits can be changed at any time, but their effect begins on the next frame boundary. The HALT
and MDIS bits in the DSPIx_MCR are the only bit values software can change while the DSPI is running.
Address: Base + 0x0000
0
1
2
3
4
5
6
7
8
R _{MST CONT_}
W ^{R SCKE}
DCONF
FRZ
MTF
E
0
RO
OE
0
Reset 0
0
0000000
Access: R/W
9
10 11 12 13 14 15
0
PCSI PCSI PCSI PCSI PCSI PCSI
S5 S4 S3 S2 S1 S0
0000000
16
R0
W
Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
CLR_ CLR_
MDIS
DIS_ DIS_
TXF RXF
TXF
RXF
SMPL_PT
0
0
0
0
0
0
w1c w1c
1
000000000000
Figure 11-3. DSPI Module Configuration Register (DSPIx_MCR)
30 31
0
HALT
01
Table 11-3 describes the fields in the DSPI module configuration register.
Table 11-3. DSPIx_MCR Field Descriptions
Field
Description
0
MSTR
Master/slave mode select. Configures the DSPI for master mode or slave mode.
0 DSPI is in slave mode
1 DSPI is in master mode
1
Continuous SCK enable. Enables the serial communication clock (SCK) to run continuously. Refer
CONT_SCKE to Section 11.8.6, Continuous Serial Communications Clock, for details.
2–3
DCONF
[0:1]
0 Continuous SCK disabled
1 Continuous SCK enabled
DSPI configuration. The following table lists the DCONF values for the various configurations.
DCONF
00
01
10
11
Configuration
SPI
Invalid value
Invalid value
Invalid value
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-7