PXD10RM Datasheet, PDF (1006/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Terms
SS
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Table 30-2. Acronyms and Abbreviations
Description
Slave Select. Signal from the SPI master to the SPI slave indicating which SPI slave device the
Master want to communicate with.
Write 1 to clear, writing a ‘1’ to this field resets the flag
30.1.3 Glossary for QuadSPI module
Table 30-3. Glossary
Term
AHB Command
Asserted
Baud Rate
Clear
Clock Phase
Clock Polarity
Deserialize
Drain
Field
FIFO entry
Fill
Frame
Host
Instruction Code
IP Command
Logic level one
Logic level zero
Negated
RX FIFO
Serialize
Set
Definition
An AHB Command is a SFM Command triggered by a read access to the address range
belonging to the memory mapped access defined in Table 30-35. Refer to Section 30.6.6.2,
AHB Bus Related Commands” for details.
A signal that is asserted is in its active state. An active low signal changes from logic level
one to logic level zero when asserted, and an active high signal changes from logic level zero
to logic level one.
Rate of data transmission in bits per second.
To clear a bit or bits means to establish logic level zero on the bit or bits.
Determines when the data should be sampled relative to the active edge of SCK
Determines the idle state of the SCK signal.
To convert data from a serial format to a parallel format.
To remove entries from a FIFO by software or hardware.
Two or more register bits grouped together.
FIFO entries and FIFO registers are used interchangeably.
To add entries to a FIFO by software or hardware.
The data content of a serial transmission. Also referred to as QuadSPI Data.
Refers to another functional block in the device containing the QuadSPI module
8 bits defining the type of command to be executed.
A IP Command is a SFM Command triggered by writing into the QSPI_MCR[IC] field.
The voltage that corresponds to Boolean true (1) state.
The voltage that corresponds to Boolean false (0) state.
A signal that is negated is in its inactive state. An active low signal changes from logic level
‘0’ to logic level ‘1’ when negated, and an active high signal changes from logic level ‘1’ to
logic level ‘0’.
First-In-First-Out buffer for received data
To convert data from a parallel format to a serial format.
To set a bit or bits means to establish logic level one on the bit or bits.
30-2
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor