PXD10RM Datasheet, PDF (788/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

22.2 Introduction
22.2.1 Overview
The LCD driver module has up to 64 frontplane drivers (n) and up to 6 backplane drivers (m) so that a
maximum of 384 LCD segments are controllable. The actual implementation (n,m) depends on the device
specification. Each segment is controlled by a corresponding bit in the LCD RAM. m multiplex modes
(1/1, 1/2,...1/m duty), and three bias (1/1, 1/2, 1/3) methods are available. The V₀ voltage is the lowest level
of the output waveform and V₃ becomes the highest level. All frontplane and backplane pins can be
multiplexed with other Port functions.
The LCD driver system consists of five major sub-modules:
• Timing and Control – consists of registers and control logic for frame clock generation, bias
voltage level select, frame duty select, contrast adjustment, backplane select and frontplane
select/enable, remapping of backplane drivers to produce the required frame frequency and voltage
waveforms.
• LCD RAM – contains the data to be displayed on the LCD. Data can be read from or written to the
display RAM at any time.
• Frontplane Drivers – consists of n frontplane drivers.
• Backplane Drivers – consists of m backplane drivers.
• Voltage Generator – Based on reference voltage, i.e. applied to VLCD, it generates the voltage
levels for the timing and control logic to produce the frontplane and backplane waveforms.
22-2
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor