PXD10RM Datasheet, PDF (430/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

12.5.1 Synchronizing to panel frame rate
Since the DCU fetches data directly from memory independently of the CPU, there is the possibility that
changes to the DCU layer configuration or content can create incoherent content on the panel. To help
avoid this situation there are five timing control flags that define when the DCU recognizes and locks
changes to its configuration. These can be used to manage changes to control descriptors, CLUT or tile
memory, or source graphics and so avoid coherency problems on the panel. All the timing flags are in the
INT_STATUS register and can be used to generate interrupts from the DCU.
The DCU configuration is completely open during the vertical blanking period and control descriptors and
some other registers may also be programmed at any time. The configuration present one HSYNC before
the end of the vertical blanking period is the configuration used by the DCU for the panel refresh phase.
The VS_BLANK and LS_BF_VS flags give indication of the start of the vertical blanking period. The
VS_BLANK flag is set at the beginning of the vertical blanking period. The LS_BF_VS flag is set a given
number of horizontal lines before the start of the vertical blanking period; the given number of lines is
defined by the LS_BF_VS bit field in the THRESHOLD register.
The PROG_END flag indicates that the DCU has locked the contents of its configuration registers for the
new panel refresh period. No further changes are accepted to the DCU configuration after this flag is set
(until the next vertical blanking period).
The DMA_TRANS_FINISH flag indicates that the DCU has completed fetching all data from memory in
the current panel refresh cycle. This normally precedes the vertical blanking period and indicates that it is
possible to change the contents of a memory that contains graphics used by the DCU.
The VSYNC flag indicates that the DCU has begun the next panel refresh period.
12.5.2 Managing the DCU FIFOs and DMA activity
The DCU fetches graphic data directly from internal and external memory using a dedicated DMA system
and manages the output of data to the TFT LCD panel such that the panel always receives the pixel
information when expected. Since the panel is sharing access to memory with the system DMA and CPU
it cannot depend on the required data always being available at all times. It therefore it uses input and
output FIFOs to temporarily store incoming and outgoing data until required and thus reduces the
opportunity for the panel to be starved of pixel data.
The DCU manages the supply of graphic data to its format conversion and blending stages using input
FIFOs that are 256 x 32 bits in size. The data that is driven to panel is managed using an output FIFO that
is 128 pixels in size. See Figure 12-1 for a diagram of the input FIFO and output FIFO operation in the
DCU
The input FIFOs are not accessible to the user but it is possible to set thresholds that control the DCU
behavior when the FIFOs are becoming full or empty and observe when the lower and higher thresholds
are reached. This can help detect and avert situations where the DCU is running out of data to send to the
panel.
The FIFO thresholds are set in the THRESHOLD_INPUT_BUF_1/2 registers. The upper thresholds are
set by the INP_BUF_Pm_HI bit fields (where m is the position of the pixel in the blend stack) and these
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor