PXD10RM Datasheet, PDF (1198/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

External IRQ
IRQ_1
Table 37-1. SIUL signal properties (continued)
Flag
EIF[8]
EIF[9]
EIF[10]
EIF[11]
EIF[12]
EIF[13]
PCR
PCR[80]
PCR[86]
PCR[87]
PCR[98]
PCR[131]
PCR[132]
Port
PF[10]
PG[0]
PG[1]
PG[12]
PK[10]
PK[11]
Package
144 176 208
x
x
x
x
x
x
x
x
x
x
x
x
—
x
x
—
x
x
37.4.1 Detailed signal descriptions
37.4.1.1 General-purpose I/O pins (GPIO[0:132])
The GPIO pins provide general-purpose input and output function. The GPIO pins are generally
multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an input
(GPDIn_n) or output (GPDOn_n) register.
37.4.1.2 External interrupt request input pins (EIRQ[0:13])¹
The EIRQ[0:13] are connected to the SIU inputs. Rising or falling edge events are enabled by setting the
corresponding bits in the SIU_IREER or the SIU_IFEER register.
37.5 Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module.
37.5.1 SIUL memory map
Table 37-2 gives an overview on the SIUL registers implemented.
Table 37-2. SIUL memory map
Address
Name
Base (0xC3F9_0000)
-
Base + 0x0004
MIDR1
Base + 0x0008
MIDR2
Base + (0x000C - 0x0013)
-
Base + 0x0014
ISR
Description
Reserved
MCU ID Register #1
MCU ID Register #2
Reserved
Interrupt Status Flag Register
Size
(bits)
Location
-
32-bit on page 6
32-bit on page 7
-
32-bit on page 9
1. EIRQ[0:11] in the 144-pin LQFP; EIRQ[0:13] in all other packages
37-4
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor