PXD10RM Datasheet, PDF (242/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 9-12. eMIOS200 Enable Channel Register (EMIOSUCDIS) Field Descriptions
Field
Description
CHDIS[n]
Enable Channel [n] bit
The CHDIS[n] bit is used to disable each of the channels by stopping its respective clock.
1 = Channel [n] disabled
0 = Channel [n] enabled
Note: Channels that occupy a pair of slots are referred to as by their lower slot number (LSB=0
standard), therefore the bits corresponding to their higher slot number are reserved and read 0.
9.4.2.5 eMIOS200 UC A Register (EMIOSA[n])
address: UC[n] base address + 0x00
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
A
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-12. eMIOS200 UC A Register (EMIOSA[n])
Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be
assigned to address EMIOSA[n]. Both A1 and A2 are cleared by reset. Figure 9-13 summarizes the
EMIOSA[n] writing and reading accesses for all operation modes. For more information see section
Section 9.5.1.1, UC Modes of Operation.
9-16
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor