PXD10RM Datasheet, PDF (648/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 17-64. PFLASH Configuration Register 0 Field Descriptions (continued)
Field
Description
B02_P0_IPFE _{Bank0+2, Port 0 Instruction Prefetch Enable. This field enables or disables prefetching initiated by an}
instruction fetch read access. This field is set by hardware reset.
0 No prefetching is triggered by an instruction fetch read access
1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch
read access
B02_P0_PFLM _{Bank0+2, Port 0 Prefetch Limit. This field controls the prefetch algorithm used by the PFLASH}
controller. This field defines the prefetch behavior. In all situations when enabled, only a single
prefetch is initiated on each buffer miss or hit. This field is set to 2b10 by hardware reset.
00 No prefetching is performed.
01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.
1- The referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on
a buffer hit (if not already present), that is, prefetch on miss or hit.
B02_P0_BFE _{Bank0+2, Port 0 Buffer Enable. This bit enables or disables page buffer read hits. It is also used to}
invalidate the buffers. This bit is set by hardware reset.
0 The page buffers are disabled from satisfying read requests, and all buffer valid bits are
cleared.
1 The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when
the buffers are successfully filled.
17.4.3.2.2 Platform Flash Configuration Register 1 (PFCR1)
This register defines the configuration associated with flash memory bank1. This typically corresponds to
the optional “data flash”. If bank1 is not present, the contents of this register are ignored. The register is
described below in Figure 17-45 and Table 17-65.
Offset 0x020
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
B1_APC
W
B1_WWSC
B1_RWSC
B1_R
WWC
Reset 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{B1_R} 0
0
0
0
0
0 _{B1_P1 B1_R} 0
0
0
0
0
0 _{B1_P0}
W ^WWC
_BFE WWC
_BFE
Reset 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1
Figure 17-45. PFLASH Configuration Register 1 (PFCR1)
17-98
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor