PXD10RM Datasheet, PDF (238/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 9-10. Global Prescaler clock divider (continued)
GPRE[0:7]
.
.
.
.
11111110
11111111
Divide ratio
.
.
.
.
255
256
9.4.2.2 eMIOS200 Global FLAG Register (EMIOSGFLAG)
The EMIOSGFLAG is a read-only register that groups the FLAG bits from all channels. This organization
improves interrupt handling on simpler devices. Each bit relates to one channel.
The two modules on this device, EMIOS0 and EMIOS1, have different structures for this register as shown
in Figure 9-6 and Figure 9-7.
For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS[n] register.
address: eMIOS0 base address +0x04
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0 F23 F22 F21 F20 F19 F18 F17 F16
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{F15 F14 F13 F12 F11 F10}
F9
F8
0
0
0
0
0
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-6. eMIOS200 Global FLAG Register (EMIOSGFLAG) for EMIOS0
9-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor